By Topic

Differential power cryptanalysis attacks against PRESENT implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Jing Zhang ; Dept. of Comput. Sci. & Eng., Shanghai Jiao Tong Univ., Shanghai, China ; Dawu Gu ; Zheng Guo ; Lei Zhang

PRESENT, proposed by A. Bogdanov et al. in CHES 2007, is an ultra-lightweight symmetric cipher for extremely constrained environments such as RFID tags and sensor networks. In this article, a representative platform, 0.25 μm 1.8 V standard cell circuit is proposed to complement the PRESENT, the simulation-based ASIC experimental environment is built to acquire power data. According to the fact that the power consumption of a digital circuit implemented in the CMOS technology depends on the data that the circuit is processing, we create the hypothetical circuit model for differential power analysis (DPA) against the special block cipher, PRESENT. Two Different statistical methods, multi-bit DPA and correlation power analysis (CPA), are conducted in this paper to analyze the power data sampled from the power traces. We can attack all secret key bits after first two rounds DPA attack. Our results present the vulnerability to power analysis attack against the hardware implementations of PRESENT.

Published in:

Advanced Computer Theory and Engineering (ICACTE), 2010 3rd International Conference on  (Volume:6 )

Date of Conference:

20-22 Aug. 2010