Referenced Items are not available for this document.
A new formal method for the specification, of real-time system requirements and their refinement to a design architecture is set out here. This integrated method is derived from a recently developed formal semantics, logic and refinement calculus for the IEEE standard hardware specification language VHDL. The specification format consists of three-phase “before, during and after” logical schemas, and comes with a combinatorial schema calculus and a refinement theory. The look and feel is reminiscent of Z and VDM and is intended to present an “upgrade path” to real-time for users with specification skills in these languages
Published in:
Real-Time Systems, 1996., Proceedings of the Eighth Euromicro Workshop on
Date of Conference: 12-14 Jun 1996
- Page(s):
- 200 - 204
- Meeting Date :
- 12 Jun 1996-14 Jun 1996
- ISSN :
- 1068-3070
- Print ISBN:
- 0-8186-7496-2
- INSPEC Accession Number:
- 5444335
- Conference Location :
- L'Aquila
- Digital Object Identifier :
- 10.1109/EMWRTS.1996.557891
- Product Type:
- Conference Publications
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