By Topic

A study of the relationship between on-chip power distribution network voltage noise, charge per clock cycle, on-chip decoupling capacitance and clock jitter in a 40-nm field programmable gate array test chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Hui Lee Teng ; Altera Corp., San Jose, CA, USA ; Shishuang Sun ; Man On Wong ; Boyle, P.
more authors

As technology process nodes continue to shrink, the performance of nano-technology devices becomes increasingly dependent on power quality. With core logic voltage reduced to 0.9 V, 40-nm devices are more susceptible to on-chip power distribution network (PDN) voltage noise. On-chip PDN voltage noise increases jitter and reduces a circuit's timing margin, which may lead to performance failures due to timing violations. This paper presents a study of the relationship between on-chip PDN voltage noise, charge per clock cycle (QCYCLE), on-chip decoupling capacitance (ODC), and internal clock period jitter. This study investigates the impact of on-chip PDN voltage noise, generated by switching internal logic elements, on jitter performance using two Altera 40-nm field programmable gate array (FPGA) test chips. The results from this study can aid chip designers in optimizing power quality, thereby achieving error-free timing design goals.

Published in:

Applications of Electromagnetism and Student Innovation Competition Awards (AEM2C), 2010 International Conference on

Date of Conference:

11-13 Aug. 2010