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Implementation of re-configurable Open Core Protocol compliant memory system using VHDL

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3 Author(s)
Ramesh Bhakthavatchalu ; Dept. of ECE, Amrita Vishwa Vidyapeetham, Amritapuri, Kollam-690525, Kerala, India ; G R Deepthy ; S. Shanooja

The design of a large scale System on Chip (SoC) is becoming challenging not only due to the complexity but also due to the use of a large amount of Intellectual Properties (IP). An interface standard for IP cores is becoming important for a successful SoC design. In a SoC the different IP cores are interfaced through different protocols. It increases the complexity of the design. Open Core Protocol (OCP) is an openly licensed core centric protocol intended to meet contemporary system level integration challenges. OCP promotes IP core reusability and reduces design time, design risk and manufacturing costs for SoC designs. OCP defines a highly configurable interface including data flow, control, verification and test signals required to describe an IP core's communication. This paper focuses on the design and implementation of a reconfigurable OCP compliant master slave interface for a memory system with burst support. An OCP compliant memory system was designed and shown that the use of OCP wrapper reduces the power and increases the speed of the system. The proposed design was implemented in VHDL and the Synthesis is done using Xilinx ISE 10.1.Experimental results are included.

Published in:

2010 5th International Conference on Industrial and Information Systems

Date of Conference:

July 29 2010-Aug. 1 2010