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An efficient I/sub DDQ/ test generation scheme for bridging faults in CMOS digital circuits

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4 Author(s)
Tzuhao Chen ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Hajj, I.N. ; Rudnick, E.M. ; Patel, J.H.

In a previous work on test generation for I/sub DDQ/ bridging faults in CMOS circuits, a genetic algorithm (GA) based approach targeting the all-pair bridging fault set stored in a compact-list data structure was used. In this paper, we target a reduced fault set, such as the one extracted from circuit layout. The reduced fault set is O(N) versus O(N/sup 2/) for the all-pair set, where N is the number of nodes in the transistor netlist. For test generation purposes, a linear-list data structure is found to be more efficient than the compact-list when a reduced fault list is targeted. We report on results for benchmark circuits that illustrate that test generation using a reduced fault list takes less time and results in more compact I/sub DDQ/ test sets with higher fault coverage of targeted bridging faults. The effects of GA sequence lengths on test generation times and test set quality are also considered.

Published in:

IDDQ Testing, 1996., IEEE International Workshop on

Date of Conference:

24-25 Oct. 1996