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A Bypass Optimization Method for Network on Chip

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5 Author(s)
Wei Hu ; Coll. of Comput. Sci., Zhejiang Univ., Hangzhou, China ; Binbin Wu ; Bin Xie ; Tianzhou Chen
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Network-on-Chip (NoC) is proposed to solve the communication bottleneck for multi-core SoC. Performance is one of the most critical feature of the NoC. Many different approaches have been introduced to improve the performance of NoC. However, most of them focus on the network part of NoC architecture and neglect other important parts of the system, especially the processor core part. This paper proposes a new architecture: a transmission bypass framework. It adds the bypass path behind the EX stage, an execution stage of the instruction pipeline, to transmit the intermediate results and save transmission time. Experimental results show that when cache misses occur, the performance of send and receive operations can be improved by 15%-38%. The performance of Splash-2 applications can be improved by 28% at most.

Published in:

Computer and Information Technology (CIT), 2010 IEEE 10th International Conference on

Date of Conference:

June 29 2010-July 1 2010

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