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Validating the design of real-time systems using a formal specification method

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2 Author(s)
Buendia-Garcia, F. ; Dept. de Ingenieria de Sistemas, Computadores y Autom., Univ. Politecnica de Valencia, Spain ; Vila-Carbo, J.

This paper proposes a method for validating the design of a real-time system. The method is based on the formal specification of the target system and the verification of its timing requirements. The main contribution consists in introducing the design issues (e.g. the tasks parameters or the scheduling algorithm) in the system specification. It will allow to check how these design issues may affect the stated timing requirements

Published in:

Real-Time Systems, 1996., Proceedings of the Eighth Euromicro Workshop on

Date of Conference:

12-14 Jun 1996