By Topic

Design and characterization of submicron BiCMOS compatible high-voltage NMOS and PMOS devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Yong Qiang Li ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada ; Salama, A.T. ; Seufert, M. ; Schvan, P.
more authors

This paper investigates the feasibility of integrating high-voltage blocking capability into a state-of-the-art submicron BiCMOS process using existing processing steps. High-voltage MOS devices fully compatible with an existing 5 V, 0.8 μm BiCMOS process have been designed and studied through extensive two-dimensional (2-D) process and device simulations. The device layout parameters in proposed high-voltage NMOS (HV-NMOS) and high-voltage PMOS (HV-PMOS) devices are optimized to achieve highest performance possible in terms of breakdown voltage and specific on-resistance with the constraints of full process compatibility. The optimized HV-NMOS and HV-PMOS devices using minimized unit-cell pitches of 7.8 and 7.3 μm achieved breakdown voltages of 129 V and specific on-resistances of 0.9 and 11.5 mn cm2, respectively. Due to their full compatibility with the existing process the high-voltage MOS devices presented in this paper can be implemented without increasing manufacturing cost. The integration of the high-voltage blocking capability into the submicron BiCMOS process can expand its application field to include high-voltage input and output (I/O) functions on the same chip with high-speed analog and high-density digital signal processing circuitry

Published in:

Electron Devices, IEEE Transactions on  (Volume:44 ,  Issue: 2 )