Referenced Items are not available for this document.
A parallel-pipelined A/D converter with an area and power efficient architecture is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-b pipeline is realized using just three amplifiers (instead of seven amplifiers with a conventional pipeline architecture). By using two such pipelines in parallel, a 52 Msamples/s prototype A/D converter that is Intended for a switched digital video application has been implemented in a 0.9-μm CMOS technology. The device occupies 15 mm 2 and dissipates 250 mW from a 5 V supply
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:32
,
Issue:
3
)
Date of Publication: Mar 1997
- Page(s):
- 312 - 320
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 5536724
- Digital Object Identifier :
- 10.1109/4.557628
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Mar 1997
- Sponsored by :
- IEEE Solid-State Circuits Society
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