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Magnetic–Electrical Interface for Nanomagnet Logic

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6 Author(s)
Shiliang Liu ; Dept. of Comput. Sci. & Eng., Univ. of Notre Dame, Notre Dame, IN, USA ; Hu, X.S. ; Nahas, J.J. ; Niemier, M.
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We present simulations of, and design alternatives for, an interface between nanomagnet logic (NML) and electrical circuitry. We propose using the fringing fields from a nanomagnet to help set the state of the free layer of a magnetic tunnel junction (MTJ). Our first magnetic-electrical interface design (MEI-1) assumes an MTJ stack layout, commonly seen in commercial magnetoresistive random access memory (MRAM). Our second design (MEI-2) is also based on a traditional MRAM process flow, but layers of the MTJ are deposited in reverse order. In MEI-2, the NML devices have the same thickness as the MTJ free layer. Simulations for MEI-2 suggest that the layer thickness and size are important design parameters, when considering realistic implementations of this MEI. By comparison, MEI-2 is applicable for the present process technology, while MEI-1 would be more easily fabricated with further technology development.

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Nanotechnology, IEEE Transactions on  (Volume:10 ,  Issue: 4 )