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Application of Enhanced Phase-Locked Loop System to the Computation of Synchrophasors

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3 Author(s)
Karimi-Ghartemani, M. ; Dept. of Electr. & Comput. Eng., Queen''s Univ., Kingston, ON, Canada ; Boon-Teck Ooi ; Bakhshai, A.

This paper introduces the application of an enhanced phase-locked loop (EPLL) system to the estimation of synchrophasors in a phasor measurement unit (PMU). The major concern is accurate estimation within off-nominal frequency operation of the system. The well-known technique based on discrete Fourier transform (DFT) can provide accurate estimation of the phasors in a three-phase balanced system. However, the negative-sequence component causes errors to the DFT estimates. The DFT cannot accomplish this task in a single-phase system. The EPLL is shown to be a solution for those shortcomings of the DFT technique, both in single-phase and in unbalanced three-phase systems, at the expense of some more complicated structure. Extensive steady-state and dynamic tests are performed and the results are presented and discussed.

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Power Delivery, IEEE Transactions on  (Volume:26 ,  Issue: 1 )