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Design and optimization of a low-power and very-high-performance 0.25-μm advanced PNP bipolar process

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1 Author(s)
B. Djezzar ; Centre de Dev. des Technol. Avancees, Algiers, Algeria

Low-power and very-high-performance 0.25-μm vertical PNP bipolar process is designed and characterized by using the mixed two-dimensional numerical device/circuit simulator (CODECS). This PNP transistor has a 25-nm-wide emitter, a 38-nm-wide base region, a current gain of 17 (without poly-Si emitter effect), and maximum cut-off frequency of 24-GHz. The conventional ECL circuits, designed by this PNP transistor, exhibit an unloaded gate delay of 22-ps at 1.75-mW, and a delay time less than 16-ps/stage for unloaded ECL ring-oscillator

Published in:

Semiconductor Conference, 1996., International  (Volume:1 )

Date of Conference:

9-12 Oct 1996