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A Novel, Variable Resolution Flash ADC with Sub Flash Architecture

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4 Author(s)
Adimulam, M.K. ; Dept. of ECE, Birla Inst. of Technol. & Sci. Pilani, Hyderabad, India ; Veeramachaneni, S. ; Muthukrishnan, N.M. ; Srinivas, M.B.

In this paper, a design for low power flash ADC with configurable resolution is proposed. A novel sub flash architecture is employed to achieve variable resolution as well as to switch the unused parallel voltage comparators and resistor bias circuit to standby mode leading to the consumption of only leakage power. The ADC is capable of operating at 4-bit, 6-bit and 8-bit precision and at a supply voltage of 1.0V, it consumes 48 mW at 8-bit, 36 mW at 6-bit and 15 mW at 4-bit resolution. The proposed ADC have been designed, compared with conventional flash ADC and verified for post layout simulations in standard 65 nm CMOS technology.

Published in:

VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on

Date of Conference:

5-7 July 2010