By Topic

Performance Analysis of 3D NoCs Partitioning Methods

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Ebrahimi, M. ; Turku Centre for Comput. Sci. (TUCS), Turku, Finland ; Daneshtalab, M. ; Liljeberg, P. ; Tenhunen, H.

3D IC design improves performance and decreases power consumption by replacing long horizontal interconnects with short vertical ones. Achieving higher performance along with reducing the network latency can be obtained by utilizing an efficient communication protocol in 3D Networks-on-Chip (NoCs). In this work, several unicast/multicast partitioning methods are explained in order to find an advantageous method with low communication latency. Moreover, two factors of efficiency, unicast latency and multicast latency, are analyzed by analytical models. We also perform simulation to compare the efficiency of proposed methods. The results show that Mixed Partitioning method outperforms other methods in term of latency.

Published in:

VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on

Date of Conference:

5-7 July 2010