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In this paper we present a new 12T loadless SRAM cell that exhibits soft error resilience characteristics. The proposed cell is based on an interlocked structure with guard gates that provides an x80 increase in soft error resilience compared to a typical unprotected 6T SRAM cell, while addressing the static power consumption issue of modern CMOS technologies. At a 90nm technology, simulations show that the investigated 12T SRAM cell draws 3 times less leakage current than a DICE cell of similarly sized transistors and 20% less than a typical 6T cell.
Date of Conference: 5-7 July 2010