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Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model

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4 Author(s)
Naoya Onizawa ; Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan ; Tomoyoshi Funazaki ; Atsushi Matsumoto ; Takahiro Hanyu

A performance-evaluation simulator, such as a cycle-accurate simulator, is a key tool for exploring appropriate asynchronous Network-on-Chip (NoC) architectures in early stages of VLSI design, but its accuracy is insufficient in practical VLSI implementation. In this paper, a highly accurate performance-evaluation simulator based on a delay-aware model is proposed for implementing an appropriate asynchronous NoC system. While the unit delay between circuit blocks at every pipeline stage is constant in the conventional cycle-accurate simulator, which causes poor accuracy, the unit delay between circuit blocks in the proposed approach is determined independently by its desirable logic function. The use of this ”delay-aware” model makes it accurate to simulate asynchronous NoC systems. As a design example, a 16-core asynchronous Spider on NoC system is simulated by the conventional cycle-accurate and the proposed simulator whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as one of the transistor-level simulators with the simulation speed comparable to the cycle-accurate simulator.

Published in:

2010 IEEE Computer Society Annual Symposium on VLSI

Date of Conference:

5-7 July 2010