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A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS

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6 Author(s)
Leshner, S. ; Arizona State Univ., Tempe, AZ, USA ; Berezowski, K. ; Xiaoyin Yao ; Chalivendra, G.
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In this paper we describe the design, simulation, fabrication, and test of a 32-bit 2's complement integer multiplier constructed from a combination of CMOS standard cells and threshold logic elements in a 65 nm low power process. As compared to a multiplier designed solely using CMOS standard cells, the threshold logic based multiplier is 1.23x smaller and consumes 1.41x less dynamic power and 2.5x less leakage power at the same process corner.

Published in:

VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on

Date of Conference:

5-7 July 2010

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