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Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT

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2 Author(s)
Srinivasan, P. ; Inst. of Microelectron. & Wireless Syst., Nat. Univ. of Ireland, Maynooth, Ireland ; Farrell, R.

Modular and hierarchical based test architecture are the two of the most common testing techniques used in complex SoC designs. However, modular test architectures uses an expensive (in terms of silicon area) test wrapper around each block. On the other hand hierarchical test architecture requires additional effort at block level to isolate each block from surrounding blocks and a TAM to perform scan compression. In this paper, we analyze the limitations of the modular test architecture. Based on the analysis, we propose a test plan for hierarchical test architecture by integrating partition chain, combinational scan compression and (RPCT) reduced pin count test. Experimental results show that approximately 50% of DFT area can be reduced using the partition chain as compared to standard test wrapper. It also demonstrates the feasibility of the proposed test plan using a commercial ATPG tool.

Published in:

VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on

Date of Conference:

5-7 July 2010