From specification validation to hardware testing: a unified method

With the great advancement in the design automation field, actual tools allow to describe hardware systems as software programs using high-level hardware description languages such as VHDL or VERILOG. Consequently, a design fault which affects the system specification can be considered as a software fault. To test the system specification against (software) design faults, we propose in this paper an adaptation of the mutation analysis, originally proposed for software testing, to test VHDL functional descriptions. The resulted test set is applied on the gate-level structure of the system to measure its capacity to uncover hardware faults such as the stuck-at faults. Heuristics to enhance the test set in order to be sufficient for testing hardware faults are presented and results are compared to traditional ATPGs. Accordingly, this paper presents a unified method for testing both the system specification and the hardware implementation.