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Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes

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7 Author(s)
Patil, N. ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA ; Lin, A. ; Jie Zhang ; Hai Wei
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We present a new very large scale integration (VLSI)-compatible metallic carbon nanotube (CNT) removal technique called VLSI-compatible metallic CNT removal (VMR) that overcomes challenges of existing techniques by combining design and processing to create carbon nanotube field effect transistors (CNFET) circuits immune to CNT imperfections such as metallic and mispositioned CNTs. Using VMR, we experimentally demonstrate combinational and sequential CNFET logic circuits such as half-adder sum generators and D-latches. These circuits form the fundamental building blocks of VLSI digital systems.

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Nanotechnology, IEEE Transactions on  (Volume:10 ,  Issue: 4 )