Digital integrated circuit testing using transient signal analysis

A novel approach to testing CMOS digital circuits is presented that is based on an analysis of I/sub DD/ switching transients on the supply rails and voltage transients at selected test points. We present simulation and hardware experiments which show distinguishable characteristics between the transient waveforms of defective and non-defective devices. These variations are shown to exist for CMOS open drain and bridging defects, located both on and off of a sensitized path.