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Gate-level modeling of leakage current failure induced by total dose for the generation of worst-case test vectors

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1 Author(s)
A. A. Abou-Auf ; US Army Res. Lab., Adelphi, MD, USA

A novel gate-level model has been developed for the automatic generation of worst-case test vectors for leakage current failure induced in CMOS devices by total dose

Published in:

IEEE Transactions on Nuclear Science  (Volume:43 ,  Issue: 6 )