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High speed latchup resistant CMOS data output buffer for submicrometre DRAM application

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1 Author(s)
Hoi-Jun Yoo ; Dept. of Electron. Eng., Kangwon Nat. Univ., Chunchon, South Korea

A latchup resistant CMOS data output buffer for 0.5 μm CMOS DRAM is designed, fabricated and measured. It has a floating n-well which adjusts its voltage level to suppress the leakage current. Its leakage current is controlled to be <10 nA with the bonding pad voltage ranging from 0 to 10 V. The propagation delay is measured to be shorter by 3.8 ns than that of an NMOS data output buffer

Published in:

Electronics Letters  (Volume:32 ,  Issue: 24 )