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Explicit Communication and Synchronization in SARC

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6 Author(s)

A new network interface optimized for SARC supports synchronization and explicit communication and provides a robust mechanism for event responses. Full-system simulation of the authors' design achieved a 10- to 40-percent speed increase over traditional cache architectures on 64 cores, a two- to four-fold decrease in on-chip network traffic, and a three- to five-fold decrease in lock and barrier latency.

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Micro, IEEE  (Volume:30 ,  Issue: 5 )