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A complete and comprehensive physics-based model for negative bias temperature instability (NBTI) reliability simulation of analogue circuits in nanometre CMOS technologies is proposed. It includes typical NBTI peculiarities, such as relaxation after voltage stress reduction, and dependence on time-varying voltage stress, temperature and frequency. Including both the recoverable and the permanent NBTI component, the model offers a significant accuracy improvement over existing compact models. It is therefore well suited for accurate circuit reliability analysis and failure-time prediction. Additionally, the model includes only 10 process-dependent parameters, enabling easy calibration. The model was validated on a 1.4 EOT CMOS process.