By Topic

NBTI model for analogue IC reliability simulation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
E. Maricau ; Department of Electrical Engineering ESATMICAS, Kasteelpark Arenberg 10, 3001 Leuven, Belgium ; G. Gielen

A complete and comprehensive physics-based model for negative bias temperature instability (NBTI) reliability simulation of analogue circuits in nanometre CMOS technologies is proposed. It includes typical NBTI peculiarities, such as relaxation after voltage stress reduction, and dependence on time-varying voltage stress, temperature and frequency. Including both the recoverable and the permanent NBTI component, the model offers a significant accuracy improvement over existing compact models. It is therefore well suited for accurate circuit reliability analysis and failure-time prediction. Additionally, the model includes only 10 process-dependent parameters, enabling easy calibration. The model was validated on a 1.4 EOT CMOS process.

Published in:

Electronics Letters  (Volume:46 ,  Issue: 18 )