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A new hierarchical genetic algorithm for low-power network on chip design

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4 Author(s)
Jinqing Qi ; Sch. of Inf. & Commun. Eng., Dalian Univ. of Technol., Dalian, China ; Hanqing Zhao ; Jing Wang ; Zhengxue Li

A new hierarchical genetic algorithm for low-power network on chip (NoC) design is proposed in this paper. As 2D-mesh is a widely used NoC topology, this paper studies the optimization of mapping IP (intellectual property) cores onto regular and irregular 2D-mesh network while minimizing communication power consumption. Experimental results show that significant energy savings can be achieved. For instance, for a given application, up to 39% energy savings have been observed.

Published in:

Intelligent Control and Information Processing (ICICIP), 2010 International Conference on

Date of Conference:

13-15 Aug. 2010