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Fault-tolerant and power-aware scheduling algorithm in hard-real-time distributed systems

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4 Author(s)
Zhu Ping ; Dept. of Comput. Sci. & Technol., HuaZhong Univ. of Sci. & Technol., Wuhan, China ; Yang Fumin ; Tu Gang ; Luo Wei

Dynamic voltage scaling (DVS) technique is being increasingly used in hard-real-time energy-limited embedded systems as a means to conserve energy and prolong their lifetimes. In this paper, we first analyze the interplay between fault-tolerance and energy-saving as well as their quantitative needs on processor slack resource. Then, we extend the traditional fault-tolerant completion time test (FTCTT) to power-aware fault-tolerant completion time test (PAFTCTT). Based on PAFTCTT, a voltage slowdown factor calculation is proposed. These slowdown factors not only guarantee that all hard tasks can be scheduled within their deadlines despite of any single permanent fault, but also effectively reduce energy consumption. Finally, the simulation experiments reveal that slowdown factor technique can achieve the percents of energy-saving up to 31.3% (with an average of 16.3%).

Published in:

Computer Science and Information Technology (ICCSIT), 2010 3rd IEEE International Conference on  (Volume:4 )

Date of Conference:

9-11 July 2010