A DFTR router architecture for 3D Network on Chip

In this paper, we proposed a dual flit transmission rate (DFTR) router architecture according to the property of short distance for the inter-wafer links for 3D Network on Chip (NoC). The equivalent bandwidth of the inter-wafer links can be N times wider than that of the intra-wafer links, since flit transmission rate in vertical direction can be N times fast than that in the horizon direction. Thus, the flits, which transfer through the DFTR router in the vertical direction, only take the 1/N time that is needed in the horizon direction. According to the performance simulation results, packet latency reduced about 20% and 40%, throughput improved about 7% and 30%, for 4×4×4 3D and 2×2×8 3D mesh network respectively, compared with the router which the vertical flit transmission rate is same with the rate in plane, when N=4.