By Topic

Deuterium post-metal annealing of MOSFET's for improved hot carrier reliability

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kizilyalli, I.C. ; Bell Labs, Lucent Technol., Orlando, FL, USA ; Lyding, J.W. ; Hess, K.

Low-temperature post-metallization anneals in hydrogen ambients are critical to CMOS fabrication technologies in reducing Si/SiO/sub 2/ interface trap charge densities by hydrogen passivation. In this letter we show that the hot carrier reliability (lifetime) of NMOS transistors can be increased by an order of magnitude when wafers are annealed in a deuterium ambient. This phenomenon can be understood as a kinetic isotope effect. The chemical reaction rates involving the heavier isotopes are reduced, and consequently, under hot electron stress, bonds to deuterium are more difficult to break than bonds to protium (H). However, the static chemical bonding (i.e., binding energies and excited states) is evidently the same for both hydrogen and deuterium. We measure identical transistor function after hydrogen and deuterium treatment before hot electron dynamics and resultant damage. Therefore, deuterium and hydrogen post-metal anneal processes are compatible with each other in semiconductor manufacturing. SIMS analysis proves that at typical anneal temperatures (400-450/spl deg/C), deuterium diffuses rapidly through the interlevel oxides and accumulates at Si/SiO/sub 2/ interfaces. Transistor speed versus reliability trade-off in CMOS device design is discussed in light of the findings of this study.

Published in:

Electron Device Letters, IEEE  (Volume:18 ,  Issue: 3 )