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FPGA Based on Integration of CMOS and RRAM

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3 Author(s)
Sansiri Tanachutiwat ; College of Nanoscale Science and Engineering, University at Albany, NY, USA ; Ming Liu ; Wei Wang

In this paper, a novel CMOS-nano hybrid reconfigurable field-prgrammable gate array architecture (rFPGA) is introduced based on resistive memory (RRAM) devices. Different from the existing crossbar-based CMOS-nano architectures, rFPGA consists of mainly 1T1R RRAM structures that can be fabricated by using a CMOS-compatible process. These devices can efficiently establish FPGA block memories. More importantly, novel RRAM routing switches are developed to replace the CMOS routing switches to achieve significant density enhancement and power reduction. The simulation results demonstrate that 2-D and 3-D rFPGAs provide at least 2× -3× overall improvement in terms of area with 20% lower power consumption, compared with the corresponding CMOS FPGAs.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:19 ,  Issue: 11 )