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A novel approach of designing serial-serial hybrid multiplier is proposed for applications with high data sampling rate ( ≥4 GHz). The conventional way of partial product formation is revamped. Our proposed technique effectively forms the entire partial product matrix in just n sampling cycles for an n × n multiplication instead of at least 2n cycles in the conventional serial-serial multipliers. It achieves a high bit sampling rate by replacing conventional full adders and 5:3 counters with asynchronous 1's counters so that the critical path is limited to only an and gate and a D flip-flop (DFF). The use of 1's counter to column compress the partial products preliminarily reduces the height of the partial product matrix from n to [log2n] +1, resulting in a significant complexity reduction of the resultant adder tree. The proposed hybrid column compressed multiplier consists of a serial-serial data accumulation unit and a parallel carry save adder (CSA) array that occupies approximately 35% and 58% less silicon area than the full CSA array multiplier with operands of wordlength 32 × 32 and 64 × 64, respectively. The post-layout simulation results based on 90-nm seven metal single poly CMOS process technology shows that our 64 × 64 multiplier dissipates 39% less average power at a sampling rate of 4 GHz, and has only 11% additional delay penalty to complete a multiplication compared to the conventional fully parallel CSA array multiplier.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:19 , Issue: 10 )
Date of Publication: Oct. 2011