A Low-Loss 50–70 GHz SPDT Switch in 90 nm CMOS

This paper presents an ultra-low-loss 50-70 GHz single-pole double-throw (SPDT) switch built using a standard 90 nm CMOS process. The switch is based on λ/4 transmission lines with shunt inductors at the output matching network. The SPDT switch results in a measured insertion loss of 1.5-1.6 dB at 53-60 GHz and <; 2.0 dB at 50-70 GHz. The measured isolation is >25 dB, and the output port-to-port isolation is > 27 dB at 50-70 GHz. The measured P1dB is 13.5 dBm with a corresponding IIP3 of 22.5 dBm at 60 GHz. The return loss is better than -8 dB at 50-70 GHz. The active chip area is 0.5 × 0.55 mm
²
and can be reduced in future designs by folding the on λ/4 transmission lines. To our knowledge, this paper presents the lowest insertion loss 60 GHz SPDT in any CMOS technology.