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A detailed system design methodology for architecting area optimized DSP sub-system for multi-channel voice gateways is presented. An architecture for a specific subsystem including memory organization and I/O bandwidth requirements is described. System level performance and characterization details of this sub-system in a 65 nm generic process are provided. It is shown that a substantial reduction of 75% in sub-system memory area is achieved with only a small increase of 17% in peak processing load.
Date of Conference: 18-21 July 2010