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A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration

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2 Author(s)
El-Chammas, M. ; Stanford Univ., Stanford, CA, USA ; Murmann, B.

A 12-GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS. The design utilizes a background timing skew calibration technique to improve dynamic performance, and comparator offset calibration to reduce power dissipation. The experimental prototype achieves an SNDR of 25.1 dB at Nyquist and 27.5 dB for low frequency inputs. The circuit occupies an active area of 0.44 mm2 and consumes 81 mW from a 1.1-V supply.

Published in:

VLSI Circuits (VLSIC), 2010 IEEE Symposium on

Date of Conference:

16-18 June 2010