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A CMOS 6-Bit 16-GS/s time-interleaved ADC with digital background calibration

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3 Author(s)
Chun-Cheng Huang ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chung-Yi Wang ; Jieh-Tsorng Wu

An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.

Published in:

VLSI Circuits (VLSIC), 2010 IEEE Symposium on

Date of Conference:

16-18 June 2010

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