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A 5Gb/s speculative DFE for 2x blind ADC-based receivers in 65-nm CMOS

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5 Author(s)
Sarvari, S. ; Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada ; Tahmoureszadeh, T. ; Sheikholeslami, A. ; Tamura, Hirotaka
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This paper presents the design of a DFE for a 2x blind ADC-based RX. The DFE is implemented in 65-nm CMOS along with a 2x blind CDR and ADC. Our measured results confirm 5Gb/s data recovery with BER less than 10-12 with a channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. Without the DFE, the BER exceeds 10-8.

Published in:

VLSI Circuits (VLSIC), 2010 IEEE Symposium on

Date of Conference:

16-18 June 2010