A 5Gb/s speculative DFE for 2x blind ADC-based receivers in 65-nm CMOS

This paper presents the design of a DFE for a 2x blind ADC-based RX. The DFE is implemented in 65-nm CMOS along with a 2x blind CDR and ADC. Our measured results confirm 5Gb/s data recovery with BER less than 10
^-12
with a channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. Without the DFE, the BER exceeds 10
^-8
.