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This interleaving energy-conservation mode control for single-inductor dual-output converter uses the superposition technique to yield the optimal average inductor current and 91% peak efficiency. Neither a freewheel stage nor a post-regulator is needed at nominal conditions. The output voltage ripple appears notably minimized over 50% by means of current interleaving at full load. The chip occupies 1.44 mm2 in 65 nm CMOS and integrates with a 3D architecture for ultra-wide band system.