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Small-defect detection in sub-100nm SRAM cells using a WL-pulse timing-margin measurement scheme

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8 Author(s)
Morita, Y. ; Device Platforms Res. Labs., NEC Corp., Sagamihara, Japan ; Nose, K. ; Noguchi, K. ; Takami, S.
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The detection of small defects in an SRAM cell with our WL-pulse timing-margin measurement scheme has been demonstrated on a 90nm 2Mb SRAM. WL-width control with a high resolution of 24.1ps and a wide range improves the sensitivity of detection for delay and SNM variations with only a 0.6% area overhead, and statistical analysis makes possible the detection of small-delay defects that, in conventional testing, would be buried due to delay variations in peripheral circuitry.

Published in:

VLSI Circuits (VLSIC), 2010 IEEE Symposium on

Date of Conference:

16-18 June 2010