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A transceiver aimed at ultra-short range wireless links uses a dual-mode architecture to achieve interference robustness at ultra-low power. The receiver uses a direct-AM detection architecture combined with a high-pass baseband filter to suppress out-of-band interferers, but is reconfigured to use a mixer-high-pass filter cascade designed to suppress in-band blockers based on a real-time BER estimate. The system consumes 300uW at 1MBps (1.75mW at 16 Mbps) and can operate with a worst-case SIR of 13dB (referred to peak power).
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Date of Conference: 16-18 June 2010