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This paper presents a novel failure prediction testing technique that is applicable for system-on-chips (SoCs). Highly reliable systems such as automobiles, aircraft or medical equipments would not allow any interruptive erroneous responses during a system operation, which might result in catastrophe. Therefore, we propose a failure prediction delay testing technique that is applied during the time when the system is not working, such as power-on/-off times. To achieve high reliability in the field, the proposed technique should take into consideration various types of aging mechanisms. Since the testing environment of voltage and temperature is uncontrollable in the field, an accurate delay measurement considering the variation due to voltage and temperature should be developed. Moreover, we propose an adaptive test scheduling that gives more test chances to more possible degrading parts for improving detecting efficiency.