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A study of Through Silicon Via impact to 3D Network-on-Chip design

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3 Author(s)
Xu, T.C. ; Dept. of Inf. Technol., Univ. of Turku, Turku, Finland ; Liljeberg, P. ; Tenhunen, H.

The adoption of a 3D Network-on-Chip (NoC) design depends on the performance and manufacturing cost of the chip. Therefore, a study of Through Silicon Via (TSV), that connects different layers of a 3D chip, is crucial. In this paper, we analysis the impact of TSV design in 3D NoCs. A 3D NoC with five layers is modeled based on modern 2D chips. We discuss the TSV number required for a 3D NoC. Different placements of half and quarter layer-layer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in full and half layer-layer connection are reduced by 5.24% and 2.18% respectively, compared with quarter design. Our analysis and experiment results provide a guideline for designing TSVs in 3D NoCs to leverage the tradeoff between performance and manufacturing cost.

Published in:

Electronics and Information Engineering (ICEIE), 2010 International Conference On  (Volume:1 )

Date of Conference:

1-3 Aug. 2010

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