Referenced Items are not available for this document.
A determinate global data transfer timing scheme will significantly reduce the complexity of global control and ease constraints on sub-modules. Such a scheme allows to construct functional modules based on an explicit performance and data flow requirement. A very low gate count hardware architecture for MPEG decoder is presented to demonstrate the concept
Published in:
Consumer Electronics, IEEE Transactions on
(Volume:42
,
Issue:
4
)
Date of Publication: Nov 1996
- Page(s):
- 1021 - 1028
- ISSN :
- 0098-3063
- INSPEC Accession Number:
- 5475478
- Digital Object Identifier :
- 10.1109/30.555857
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Nov 1996
- Sponsored by :
- IEEE Consumer Electronics Society
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