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In the downlink module of Orthogonal Frequency Division Multiple Access (OFDMA) system, there is needed an alterable points FFT processor. Therefore, it is meaningful to design a FFT processor for the FFT processor which input data points could be alterable. In this paper the variable input FFT processor is designed to meet the requirements of OFDMA system. For this, in this paper we select the 2D Fourier transform algorithm as the kernel algorithm, use VHDL language to present in detail a design of two-stage pipeline structure, use QuartusII and ModelSim SE for the simulation, and verify on the EP3C25Q240C8N chip FPGA. Simulation results show that the way of implementation and design is right and meet the IEEE802.16e standard, at the same time the data precision is 16 bits, limit the clock frequency of 100 MHz, the overall timing design stability, and it could reach the scope of real-time processing.