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Notice of Violation of IEEE Publication Principles
Design of Monolithic Low Dropout Regulator for Wireless Powered Brain Cortical Implants Using a Line Ripple Rejection Technique

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2 Author(s)
Chen Zheng ; Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ, USA ; Dongsheng Ma

Notice of Violation of IEEE Publication Principles

"Design of Monolithic Low Dropout Regulator for Wireless Powered Brain Cortical Implants Using a Line Ripple Rejection Technique"
by C. Zheng and D. Ma
in the IEEE Transactions on Circuits and Systems II: Express Briefs, Vol 57, No 9, September 2010, pp. 686-690

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.

This paper has copied basic circuit structure in Figure 4 as well as portions of text from the paper cited below that were paraphrased without sufficient attribution.

"A 25mA 0.13??m CMOS LDO Regulator with Power-Supply Rejection Better Than ???56dB up to 10MHz Using a Feedforward Ripple-Cancellation Technique"
by Mohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari, Edgar S??nchez Sinencio,
in the Proceedings of the International Solid-State Circuit Conference, February 2009, pp. 330-331

This brief introduces an integrated low dropout regulator for wireless powered brain cortical implants. A line ripple rejection technique is employed to improve the line regulation of the regulator. A fast transient response is ensured to accommodate frequent changes of workload and power. The system is stabilized over the entire load range without using any external compensation capacitors. System modeling and theoretical analysis are conducted to offer a systematic study on the proposed structure. The regulator was fabricated with an IBM 130-nm CMOS process. The active die area is 0.025 mm2. Experimental results show that the power supply rejection ratio remains above 52.8 dB within the interested frequency band. The line regulation is controlled below 0.44% throughout the full input range. The output voltage can recover within 69 ns from a full load current change, with a less than 8.1-mV voltage droop.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:57 ,  Issue: 9 )