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Distributed Parametric Resonator: A Passive CMOS Frequency Divider

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2 Author(s)
Wooram Lee ; Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA ; Afshari, E.

We present an electrical distributed parametric oscillator to realize a passive CMOS frequency divider with low phase noise. Instead of using active devices, which are the main sources of noise and power consumption, an oscillation at half of the input frequency is sustained by the parametric process based on nonlinear interaction with the input signal. To show the feasibility of the proposed approach, we have implemented a 20-GHz frequency divider in a 0.13-μm CMOS process. Without any dc power consumption, 600-mV differential output amplitude is achieved for an input amplitude of 600 mV. The input frequency ranges from 18.5 to 23.5 GHz with varactor tuning. The output phase noise is almost 6 dB lower than that of the input signal for all offset frequencies up to 1 MHz. There is a good agreement among analysis, simulation, and 10-MHz measurement results. To the best of our knowledge, this is the first passive frequency divider in a CMOS process.

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Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 9 )