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A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS

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4 Author(s)
Hong Chang Yeoh ; Sch. of Electr. & Electron. Eng., Chung-Ang Univ., Seoul, South Korea ; Jae-Hun Jung ; Yun-Hwan Jung ; Kwang-Hyun Baek

This paper presents a low-power direct digital frequency synthesizer (DDFS) based on a hybrid design with a maximum operating frequency of 1.3 GHz. The proposed hybrid design is capable of extending the resolution of traditional nonlinear digital-to-analog converter (DAC)-based DDFS by adding a linear slope component to the approximated sine wave produced from a nonlinear DAC via an additional linear DAC. With an 11-bit combined DAC, the prototype DDFS produces a minimum spurious free dynamic range (SFDR) of 52 dBc from dc up to Nyquist frequency when clocked at 1.3 GHz. This 90-nm CMOS chip occupies 2 mm2 including bond pads and dissipates 350 mW with a 1.2-V digital supply and 2.5-V analog supply. The FOM of this chip is measured at 1207.9 GHz ·2 ENOB /W .

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 9 )