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The use of multiple power supplies with different output voltages has a great advantage in that it makes it possible to realize high performance ULSIs with low power dissipation. This paper presents a high-speed low-power SRAM that employs three power supplies (1, 2, and 3.3 V). A 1-V power supply is mainly used in the SRAM core to save standby and/or active power, while a 2-V supply is used in critical components to realize high performance. The voltage applicable to each MOSFET is up to 2.2 V because of the use of a 5-nm ultrathin gate oxide, and so the 3.3-V power supply is used only for LV-TTL level I/O buffers. Secure write operation for 1-V six-transistor memory cells is guaranteed by using a new switched powerline impedance scheme. To reduce dynamic write power dissipation, a segmented bitline scheme is adopted and long global bitlines are assigned to the 4th (topmost) metal layer. The data stored in memory cells are read out via virtual-GND lines by sensing the change in current volume. The practical use of parasitic bipolar action in SOI MOSFETs is being actively considered as a way of obtaining a large read current from memory cells. In addition, a 1-V double-rail bidirectional intradatabus is developed for transferring multibit high-speed data between the SRAM core and I/O buffers. A 32K-word × 9-bit SRAM chip, fabricated with the 0.2-μm-gate CMOS/SIMOX process, has achieved a 7.5-ns address access time for 65-pF external loads. The power dissipation during standby is less than 0.3 mW and the values for 100-MHz operation are 5.8 mW (write) and 11.0 mW (read), excluding that of the 3.3-V I/O buffers.