By Topic

A dual core oxide 8T SRAM cell with low Vccmin and dual voltage supplies in 45nm triple gate oxide and multi Vt CMOS for very high performance yet low leakage mobile SoC applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

21 Author(s)
Ping Liu ; Qualcomm Inc, 5775 Morehouse Drive, San Diego, CA 92121, USA ; Joseph Wang ; Michael Phan ; Manish Garg
more authors

In this work we have demonstrated, for the first time, a 0.605μm2 dual core oxide (DCO) dual Vdd 8T SRAM cell in 45 LPG triple gate oxide CMOS process for use as L1 cache for high performance low leakage mobile applications. The DCO 8T SRAM operates under dual voltage supplies with write assist. Compared to traditional single-end 8T cell, DCO 8T SRAM showed the same performance with only half the standby leakage, and lower Vccmin. The PU Vt and dual core oxide boundary were optimized to achieve robust Vccmin, process margin and reliability. The 45 LPG thin core transistors and the DCO 8T SRAM are able to achieve 1.5 GHz speed with ~500mW at 0.9 V and a low Vccmin of 0.6 V.

Published in:

2010 Symposium on VLSI Technology

Date of Conference:

15-17 June 2010