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In this work we have demonstrated, for the first time, a 0.605μm2 dual core oxide (DCO) dual Vdd 8T SRAM cell in 45 LPG triple gate oxide CMOS process for use as L1 cache for high performance low leakage mobile applications. The DCO 8T SRAM operates under dual voltage supplies with write assist. Compared to traditional single-end 8T cell, DCO 8T SRAM showed the same performance with only half the standby leakage, and lower Vccmin. The PU Vt and dual core oxide boundary were optimized to achieve robust Vccmin, process margin and reliability. The 45 LPG thin core transistors and the DCO 8T SRAM are able to achieve 1.5 GHz speed with ~500mW at 0.9 V and a low Vccmin of 0.6 V.
VLSI Technology (VLSIT), 2010 Symposium on
Date of Conference: 15-17 June 2010