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Development of sub 10-µm ultra-thinning technology using device wafers for 3D manufacturing of terabit memory

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12 Author(s)
Maeda, N. ; Sch. of Eng., Univ. of Tokyo, Tokyo, Japan ; Kim, Y.S. ; Hikosaka, Y. ; Eshita, T.
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200-mm and 300-mm device wafers were successfully thinned down to less than 10-μm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50-nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9-μm, switching charge showed no change by the thinning process. CMOS logic device wafers thinned to 7-μm indicated neither change m Ion current nor junction leakage current. Thinning such wafers to <;10-μm will allow for lower aspect ratio less than 4 of Through-Silicon-Via (TSV) in a via-last process.

Published in:

VLSI Technology (VLSIT), 2010 Symposium on

Date of Conference:

15-17 June 2010