Referenced Items are not available for this document.
Minimization of threshold voltage variation to A
We have successfully suppressed threshold voltage variations due to pattern effect problems and random dopant fluctuation (RDF) using an integrated FSP-FLA technology. The serious problem of the pattern effect in FLA can be solved by using a light-absorber carbon film process, together with FSP-FLA. We estimated the temperature range in our test chip was within 10°C, being the same level obtained with spike RTA. In addition, the diffusion-less feature of FLA reduces the RDF of NMOS down to the same level as with PMOS. By applying several optimized processes, including a high-k/metal gate stack, we achieved AVT as 1.3mVμm for NMOS and 1.2mVμm for PMOS.
Published in:
VLSI Technology (VLSIT), 2010 Symposium on
Date of Conference: 15-17 June 2010
- Page(s):
- 71 - 72
- E-ISBN :
- 978-1-4244-5450-1
- Print ISBN:
- 978-1-4244-5451-8
- INSPEC Accession Number:
- 11488234
- Conference Location :
- Honolulu
- Digital Object Identifier :
- 10.1109/VLSIT.2010.5556116
- Product Type:
- Conference Publications
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